Validated open model · v0.9.0 · verified 28 July 2026

Unified BESS control, from grid following to island support and back.

The released MATLAB and Simulink reference turns the published operating concept into an explicit eight-state supervisor, a deterministic averaged plant, eight validation scenarios, and 31 focused automated tests.

What shipped

A reviewable control reference with explicit boundaries.

This is a transparent engineering translation of the IECON 2022 publication. Source-backed statements, derived quantities, and project-defined assumptions are separated in the repository ledger instead of being blended into an unsupported reproduction claim.

Modes

Eight explicit supervisor states

Grid following, island preparation, grid forming, islanded support, synchronization, reconnect preparation, recovery, and fault-safe behavior are observable and testable.

Plant

Averaged dq dynamics

A 10 MVA, 690 V, 50 Hz reference uses dynamic d/q current states, active and reactive power measurement, a PCC voltage response, grid breaker, and local-load profiles.

Interlocks

Limits before reconnection

The breaker cannot close until voltage mismatch is within 5%, frequency mismatch within 0.1 Hz, phase mismatch within 5°, and validity and readiness flags are true.

Evidence

Commit-bound validation

The v0.9.0 release records 18 top-level repository checks, 31 focused BESS tests, eight passing scenarios, zero Code Analyzer messages, and the exact validated commit SHA.

Architecture and evidence

One common measurement and limit path across both control modes.

The Simulink shell is generated entirely from MATLAB source. It wires scenario inputs to the shared controller and averaged plant kernels, exposes 20 observable signals, compiles, and is checked against the independent MATLAB simulation for every scenario.

Architecture diagram showing measurement conditioning and an eight-state supervisor selecting grid-following or grid-forming control before common limits, averaged converter and PCC plant, and validation outputs

Original unified-controller architecture

Scenario E validation traces showing synchronization error closing within voltage, frequency, and phase thresholds before breaker reconnection and return to grid-following control

Scenario E synchronization and reconnection evidence

State-flow boundary

Supervisor transitions remain observable before they can command the breaker.

Nominal islanding and reconnection path

01Grid followingP/Q control with the grid present
02Island preparationOpen breaker and condition the transition
03Grid formingEstablish voltage and frequency reference
04Island supportBalance the local-load scenario
05SynchronizationClose voltage, frequency, and phase mismatch
06Reconnect preparationRequire validity, readiness, and interlock gates
07RecoveryReturn through bounded references to grid following

Control interfaces

References, measurements, limits, and status are explicit.

References and commands

Active power, reactive power, voltage, frequency, grid-present state, breaker command, load demand, available DC power, and fault injection.

Measured outputs

P, Q, PCC voltage, frequency, phase, current, breaker state, supervisor state, commanded references, and synchronization mismatches.

Status outputs

Controller ready, synchronization ready, saturated, faulted, and measurement-valid flags support assertion-based review and safe-state checks.

Common limits

A circular P/Q current limiter, command slew limits, DC-availability constraints, finite invalid-measurement sentinels, and forming-control anti-windup bound every case.

Repository-generated scenario evidence

Transitions, reconnection, and saturation retain their source plots.

Scenario C traces showing grid loss, breaker opening, ordered transition to grid-forming control, active and reactive power, PCC voltage, frequency, and supervisor state — Scenario C · repository generated
Grid-loss transition
Grid loss opens the breaker and moves through the ordered supervisor path into island support while measured outputs remain finite and bounded by the stated scenario.
Source
v0.9.0 · a77d8cda9920 · generated by `generate_bess_validation_evidence`
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Scenario E traces showing voltage, frequency, and phase synchronization errors entering their gates before breaker reconnection — Scenario E · repository generated
Synchronization before reconnection
The breaker interlock waits for voltage mismatch within 5%, frequency mismatch within 0.1 Hz, phase mismatch within 5°, and valid ready flags.
Source
v0.9.0 · a77d8cda9920 · generated by `generate_bess_validation_evidence`
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Scenario F traces showing infeasible active and reactive power demand, current-circle saturation, anti-windup, and recovery — Scenario F · repository generated
Current limit and recovery
An infeasible P/Q request activates the common current circle and forming-control anti-windup before controlled recovery.
Source
v0.9.0 · a77d8cda9920 · generated by `generate_bess_validation_evidence`
Download source PNG Inspect focused tests

Scenario coverage

Eight deterministic regressions exercise normal, transition, limit, and fault behavior.

A · PASS

Grid-following baseline

Separate P and Q steps, bounded current, steady tracking, and stable internal states.

B · PASS

Grid disturbance

Voltage dip and frequency disturbance with bounded response and source-case recovery.

C · PASS

Grid loss

Breaker opening, ordered transition into grid-forming island support, finite signals, and no unintended closure.

D · PASS

Islanded load step

Load increase and decrease with power balance plus bounded voltage and frequency recovery.

E · PASS

Re-synchronization

Breaker interlock holds until voltage, frequency, phase, validity, and readiness gates are all satisfied.

F · PASS

Saturation

Infeasible P/Q demand activates the current circle, anti-windup, finite outputs, and controlled recovery.

G · PASS

Measurement fault

Invalid and stale measurements produce deterministic fault-safe behavior and recovery after clearing.

H · PASS

Boundary conditions

Phase offset, power availability, maximum references, zero references, and parameter validation boundaries.

Reproduce

Build the model and rerun the evidence without manual block placement.

Clone the tagged repository, start MATLAB in its root, and run the complete verification entry point:

addpath('examples/bess-unified-control'); run_all_checks(true);

Regenerate the disposable Simulink model from MATLAB source:

modelPath = build_bess_unified_control_model();

Requirements and traceability

Stable requirement IDs map operating modes, interfaces, scenarios, and evidence to implementation and automated tests.

Review the matrix

Reproduction guide

Exact build, single-scenario, full-suite, model-regeneration, and evidence-generation commands are documented together.

Open the guide

Machine-readable results

The release asset identifies merge commit a77d8cda…, MATLAB R2026a Update 4, 31 tests, eight scenarios, and per-scenario metrics.

Download results.json

Source and assumptions

The ledger distinguishes direct source statements, derived engineering quantities, and replaceable project assumptions.

Inspect source boundaries

Scope and limitations

Useful for review and extension—not plant qualification.

The paper does not disclose complete equations, gains, plant parameters, solver settings, transition timing, synchronization gates, limits, or initial conditions; replacements are labeled PROJECT_ASSUMPTION.
The plant is a deterministic averaged dq/filter-equivalent validation model, not a switching converter, electromagnetic transient network, detailed battery/DC-link model, or protection study.
The source-discussed VSG/swing/governor variant is excluded; the release implements the grid-following and stiff grid-forming research translation described in its ledger.
The Simulink shell reuses the shared MATLAB controller kernels. Wrapper parity proves wiring, timing, and workspace behavior; independent analytic tests cover transforms, P/Q signs, droop, limits, synchronization, base values, and anti-windup.
This release is not a protection system, grid-code certification model, hardware qualification, or substitute for project-specific SIL, HIL, commissioning, and safety validation.

Documentation map

Go directly to implementation, evidence, and source boundaries.

Parent and related context

Review the source, assumptions, tests, and release evidence before adapting the controller. Open verified release Verify publication DOI